PC Engines apu coreboot Open Source Firmware v4.10.0.2

1. Rebased with official coreboot repository commit 64c14b5.

2. Added soft reset feature for SuperIO GPIOs. With every platform boot SuperIO GPIOs are set to default state: input and open-drain.

3. Support IO Base Address mode for SuperIO GPIOs. SuperIO GPIOs can be controlled now in two ways:

   • through configuration registers
   • through direct access to I/O register with base address 0x220

   Both methods work in parallel without any disruptions.

Key changes - Legacy

1. Added ACPI support for GPIOs. Details are available in apu2-documentation. So far access to GPIOs was possible only via dedicated driver. Now, there is support via Linux kernel sysfs including:

   • LEDs
   • S1 switch button with interrupts
   • SIMSWAP

2. Fixed SD 3.0 mode to be runtime configurable now.

3. Added soft reset feature for SuperIO GPIOs. With every platform boot SuperIO GPIOs are set to default state: input and open-drain.

4. Support IO Base Address mode for SuperIO GPIOs. SuperIO GPIOs can be controlled now in two ways:

   • through configuration registers
   • through direct access to I/O register with base address 0x220

   Both methods work in parallel without any disruptions.

Community

Patches sent for review:

• Fix AMDFW outside CBFS
• SuperIO Nuvoton NCT5104D GPIO soft reset
• SuperIO Nuvoton NCT5104D enable Base Address mode
• Fill PC Engines apu2 SMBIOS type 16 and 17
• Adjust AGESA.h headers to AGESA version used in apu2
• Default SATA in AHCI mode for apu2

Statistics

The chart shows the total files changed from release tag against the rebase point of given release specified in CHANGELOG (CHANGELOG.md and gitlab-ci.yml excluded from statistics). Check the statistics with:

The chart represents the total line added and deleted on the PC Engines coreboot fork against the rebase point for a given release. Check the statistics with:

Two files have not been included in the diff as mentioned above since they are not a part of coreboot tree.

Testing

• PC Engines hardware configuration matrix - hardware configurations available for testing in 3mdeb laboratory.

• PC Engines release validation results - please note there are separate sheets for each board-release.

• improved coreboot flashing test with FTP server option
• fixed the python modules deprecation warning in the test infrastructure
• started the migration of test infrastructure to python3

Aggregated test results

• Mainline:

  • PASSED: 424 (-1)
  • FAILED: 13 (+1)
  • PASSED [%]: 97.03% (-0.22%)

• Legacy:

  • PASSED: 372 (no changes)
  • FAILED: 10 (no changes)
  • PASSED [%]: 97.38% (no changes)

This release does not have tests changes, therefore there is nearly no difference in the aggregated statistics. Slightly worse tests performance on FAILED tests results from the on-going USB detection problem.

Regression issue table

Download the latest firmware

What we planned

1. Improve the support of TPM2 in coreboot and SeaBIOS. Currently there is only the TCPA (TPM1.2) log support in coreboot. Additionally SeaBIOS overwrites existing entries in TPM2 log area. cbmem utility also lacks support for displaying TPM2 log area.

   WORK IN PROGRESS

2. Validate ESXi 6.7. We have got information that booting ESXi 6.7 U2 fails on apu2 and are investigating the issue.

   WORK IN PROGRESS

3. Fix bugs related to Nuvoton NCT5104D reset and implement GPIO access improvements.

   DONE

4. Reorganize runtime configuration by making it persistent across updates and accessible from user space. Also prepare a tool for offline binary modification.

   WORK IN PROGRESS

5. Vital Product Data (VPD) support. User will have possibility to store and change VPD configuration in Read-Write section of SPI flash. Moreover, default VPD keys and values will be stored in Read-Only region to protect data against corruption. Also, sortbootorder runtime configuration will be stored in VPD Read-Write section, so access to it will be possible in OS via dedicated util.

   WORK IN PROGRESS

Coming soon

Feature and improvements on the roadmap:

1. Improve the support of TPM2 in coreboot and SeaBIOS. Currently there is only the TCPA (TPM1.2) log support in coreboot. Additionally SeaBIOS overwrites existing entries in TPM2 log area. cbmem utility also lacks support for displaying TPM2 log area.
2. Validate ESXi 6.7. We have got information that booting ESXi 6.7 U2 fails on apu2 and are investigating the issue.
3. Reorganize runtime configuration by making it persistent across updates and accessible from user space. Also prepare a tool for offline binary modification.
4. Vital Product Data (VPD) support. User will have possibility to store and change VPD configuration in Read-Write section of SPI flash. Moreover, default VPD keys and values will be stored in Read-Only region to protect data against corruption. Also, sortbootorder runtime configuration will be stored in VPD Read-Write section, so access to it will be possible in OS via dedicated util.