November 2019 Newsletter
The main PIC Events and News from JePPIX partners
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During the Dutch Design Week, Florian Lemaitre and Marija Trajkovic from Eindhoven University of Technology illustrated how integrated photonic chips are created and how they might revolutionize our daily lives in the near future.
Listen to the podcast where they explain their work and exhibition.
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Microsoft Research using the JePPIX platform for fast prototyping
Dr. Kai Shi from Microsoft Research presented their post deadline paper (PDP) ‘System Demonstration of Nanosecond Wavelength Switching with Burst-mode PAM4 Transceiver’ during ECOC 2019. This PDP session drew an audience of over 200 people, with a broad expertise and key representatives from both industry and academia.
Kai Shi explained how their project greatly benefitted from generic fabrication technology as offered by the JePPIX platform. To make optimal use of PICs, Microsoft Research joined the JePPIX PIC Design Course in 2017, used an AWG design from Bright Photonics, and the Fraunhofer HHI InP platform. Finally, PIXAPP was used for packaging of the PIC. Using only foundry provided standard building blocks effectively enabled them to have a short development and prototyping cycle.
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New Partner: III-V Lab joins JePPIX
JePPIX is happy to announce a new partner: since November, III-V Lab has joined the consortium. III-V Lab is an industrial research laboratory, jointly owned by Nokia, Thales and CEA. It conducts R&D activities in the field of micro-/nano-electronics and photonics semiconductor components for different applications, such as telecoms, defence and space.
The company develops a wide range of components, relying on a high level of expertise and advanced facilities in III-V material growth and processing and their integration on silicon. The lab also has the capacity to produce limited quantities of epitaxial wafers, components, models and subsystems. This allows III-V Lab to address the rapid evolution of the market in a flexible way, offering members and partner industrial companies an early access to the components for their system development and even preliminary deployment.
Within JePPIX, III-V Lab will join R&D activities and is creating a PDK for their PIC foundry service, in this way promoting the open access ecosystem. Mohand Achouche, director of III-V Lab, already joined the latest steering committee meeting on the 7th of November, marking the start of III-V Lab's partnership within JePPIX.
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MPW Checklist - Your guide through the design flow
A typical chip production cycle consists of activities in design, fabrication, test, chip packaging, and package test. Frequently, new users of the JePPIX platforms see these elements as disconnected stages to be ticked off in sequence. Such an approach can lead to significantly extended timescales compared to what was originally expected by the user, compromised circuits and a significant increase in costs.
JePPIX now offers a new tool: the MPW Checklist. This list is designed to help the new user identify how they can plan their own development cycle, what they can do for themselves, what training is available to support them and when they should ask for it, and what other support services they may need. This checklist will be relevant to all users new to the JePPIX platforms, regardless of expertise.
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JePPIX PIC Design Course 2019 successfully finished
As every year, in 2019 Eindhoven University of Technology hosted another JePPIX PIC Design Course. The course was attended by 35 participants who considered it a great success. In this year's course, hands-on work in the cleanroom and the measurement labs was added. Participants learnt how to handle PICs, how to couple fibres, probe chips and do measurements, as well as how to pattern a hard mask on a wafer by manipulating the wafers themselves.
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Our participants were excited about the organization and the topics addressed in the course. The three JePPIX foundries also announced a special offer for the course participants, so we hope to welcome new PIC designs from them for our MPW runs soon! In the meantime, we will work hard on setting up a new edition for 2020.
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JePPIX and its Pilot Line at ECOC2019
The JePPIX InPulse Pilot Line was present at ECOC Exhibition 2019 on September 22-26, exhibiting its InP wafers from the MPW (multi project wafer) runs. Furthermore, JePPIX was represented at the 10th European Photonic Integration Forum (EPIF) at ECOC on September 24. Here, Dr. Kai Shi from Microsoft spoke about ‘Prototyping of a sub-nanosecond wavelength switching source using JePPIX’.
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Prof. Dries van Thourhout from Ghent University also spoke at the 10th EPIF. He talked about ‘New materials for advanced silicon photonics based transceivers’. JePPIX exhibited at Booth No. 402 along with the PIXAPP Pilot Line, PASSION and EPIC (European Photonics Industry Consortium).
Read more.
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IPSR-I 2020 Overview now available online
The Integrated Photonics Systems Roadmap - International (IPSR-I) 2020 overview was published on October 10, 2019. The roadmap is a joint initiative of the AIM Academy and PhotonDelta, with the objective to establish and sustain a trust based global network of industrial and R&D partners, who are working together on defining and creating future PIC technology and systems requirements.
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JePPIX is also engaged in roadmapping to connect users, suppliers and stakeholders in the PIC eco-system, and we're happy to share this IPSRI-I 2020 overview with our readers, while we work on our next JePPIX Roadmap edition.
Read the IPSR-I 2020 Overview here.
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Software Updates
Luceda Photonics
The IPKISS design platform from Luceda Photonics has recently added the Fraunhofer HHI PDK to their portfolio.
Nazca
Per designers request Bright Photonics has extended the Nazca RF-line capabilities for the Smart Photonics and Fraunhofer HHI platforms with a number of very useful features in the new Nazca release 0.5.7. The three most important ones are:
- RF-lines can be defined in a single definition and access all Nazca interconnect functionality for efficient assisted PIC routing;
- Different types of RF-lines can be connected seamlessly by a single command;
- New Nazca design rule checks assist the designer in validating the new RF-line placement.
Read more in the tutorial.
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Schedule of the next Multi-Project Wafer Runs
Apply for one of the next MPW runs from Fraunhofer HHI, SMART Photonics or LioniX International. The updated production schedule is available on our website.
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Need support with your PIC?
PICS4All has 9 Application Support Centres (ASCs) specialised in integrated photonics. We can help you with your PIC from idea to prototype. PICS4All specialists offer their support to academia, research institutes, SMEs and larger companies. Contact us at pics4all@jeppix.eu.
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